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1 mitsubishi lsis m5m417400cj,tp-5,-6,-7,-5s,-6s,-7s fast page mode 16777216-bit (4194304-word by 4-bit) dynamic ram description this is a family of 4194304-word by 4-bit dynamic rams, fabricated with the high performance cmos process, and is ideal for large-capacity memory systems where high speed, low power dissipation, and low costs are essential. the use of double-layer metal process combined with twin-well cmos technology and a single-transistor dynamic storage stacked capacitor cell provide high circuit density at reduced costs. multiplexed address inputs permit both a reduction in pins and an increase in system densities. features xx=j, tp ? standard 26 pin soj, 26 pin tsop ? single 5v 10% supply ? low stand-by power dissipation 5.5mw(max) ..................................cmos input level 2.2mw (max)* ...............................cmos input level ? low operating power dissipation m5m417400cxx-5,-5s .................... 800.0mw (max) m5m417400cxx-6,-6s .................... 660.0mw (max) m5m417400cxx-7,-7s .................... 580.0mw (max) ? self refresh capability * self refresh current ................................ 200.0 m a(max) ? fast-page mode, read-modify-write, ras -only refresh ?cas before ras refresh, hidden refresh capabilities early-write mode and oe to control output buffer impedance ? all inputs, output ttl compatible and low capacitance ? 2048 refresh cycles every 32ms (a 0 ~ a 10 ) *applicable to self refresh version (m5m417400cj,tp-5s,-6s, -7s :option) only application main memory unit for computers, microcomputer memory, refresh memory for crt pin description pin configuration (top view) outline 26p0d-b (300mil soj) outline 26p3d-e (300mil tsop) nc: no connection type name ras access time (max.ns) cas access time (max.ns) address access time (max.ns) oe access time (max.ns) cycle time (min.ns) power dissipa- tion (typ.mw) m5m417400cxx-5,-5s 50 13 25 13 90 655 m5m417400cxx-6,-6s 60 15 30 15 110 540 m5m417400cxx-7,-7s 70 20 35 20 130 475 pin name function a 0 ~ a 11 address inputs dq 1 ~ dq 4 data inputs / outputs ras row address strobe input cas column address strobe input w write control input oe output enable input v cc power supply (+5v) v ss ground (0v)
mitsubishi lsis m5m417400cj,tp-5,-6,-7,-5s,-6s,-7s fast page mode 16777216-bit (4194304-word by 4-bit) dynamic ram 2 function the m5m417400cj,tp provide, in addition to normal read, write, and read-modify-write operations, a number of other functions, e .g., fast page mode, ras -only refresh, and delayed-write. the input conditions for each are shown in table 1. table 1 input conditions for each mode note: act: active, nac: nonactive, dnc: dont care, vld: valid, ivd: invalid, apd: applied, opn: open block diagram operation inputs input/output refresh remark ras cas w oe row address column address input output read act act nac act apd apd opn vld yes fast page mode identical write (early write) act act act dnc apd apd vld opn yes write (delayed write) act act act dnc apd apd vld ivd yes read-modify-write act act act act apd apd vld vld yes ras -only refresh act nac dnc dnc apd dnc dnc opn yes hidden refresh act act nac act apd dnc opn vld yes self refresh act act nac dnc dnc dnc dnc opn yes cas before ras refresh act act nac dnc dnc dnc dnc opn yes stand-by nac dnc dnc dnc dnc dnc dnc opn no
mitsubishi lsis m5m417400cj,tp-5,-6,-7,-5s,-6s,-7s fast page mode 16777216-bit (4194304-word by 4-bit) dynamic ram 3 absolute maximum ratings recommended operating conditions (ta = 0 ~ 70c, unless otherwise noted) (note 1) note 1: all voltage values are with respect to v ss . **: v il(min.) is -2.0v when undershoot width is less than 25ns. (undershoot width is with respect to v ss .) electrical characteristics (ta = 0 ~ 70c, v cc = 5v 10%, v ss = 0v, unless otherwise noted) (note 2) note 2: current flowing into an ic is positive, out is negative. 3: i cc1 (av), i cc3 (av), i cc4 (av) and i cc6 (av) are dependent on cycle rate. maximum current is measured at the fastest cycle rate. 4: i cc1 (av) and i cc4 (av) are dependent on output loading. specified values are obtained with the output open. symbol parameter conditions ratings unit v cc supply voltage with respect to v ss -1 ~ 7 v v i input voltage -1 ~ 7 v v o output voltage -1 ~ 7 v i o output current 50 ma p d power dissipation ta = 25c 1000 mw t opr operating temperature 0 ~ 70 c t stg storage temperature -65 ~ 150 c symbol parameter limits unit min nom max v cc supply voltage 4.5 5 5.5 v v ss supply voltage 0 0 0 v v ih high-level input voltage, all inputs 2.4 5.5 v v il low-level input voltage, all inputs -1.0** 0.8 v symbol parameter test conditions limits unit min typ max v oh high-level output voltage i oh = -5.0ma 2.4 v cc v v ol low-level output voltage i ol = 4.2ma 0 0.4 v l oz off-state output current q floating 0v v out 5.5v -10 10 a i i input current 0v v in 5.5v, other inputs pins = 0v -10 10 a i cc1(av) average supply current m5m417400c-5,-5s ras , cas cycling 145 from v cc , operating m5m417400c-6,-6s t rc = t wc = min. 120 ma (note 3,4) m5m417400c-7,-7s output open 105 i cc2 supply current from v cc , stand-by (note 5) ras = cas = v ih , output open 2 ma ras = cas 3 v cc -0.2v 0.5 average supply current m5m417400c-5,-5s ras cycling, cas = v ih 145 i cc3 (av) from v cc , refreshing m5m417400c-6,-6s t rc = min. 120 ma (note 3) m5m417400c-7,-7s output open 105 average supply current m5m417400c-5,-5s ras = v il , cas cycling 80 i cc4 (av) from v cc , fast-page-mode m5m417400c-6,-6s t pc = min. 70 ma (note 3,4) m5m417400c-7,-7s output open 60 average supply current from v cc , m5m417400c-5,-5s cas before ras refresh cycling 145 i cc6 (av) cas before ras refresh mode m5m417400c-6,-6s t rc = min. 120 ma (note 3) m5m417400c-7,-7s output open 105
mitsubishi lsis m5m417400cj,tp-5,-6,-7,-5s,-6s,-7s fast page mode 16777216-bit (4194304-word by 4-bit) dynamic ram 4 capacitance (ta = 0 ~ 70c, v cc = 5v 10%, v ss = 0v, unless otherwise noted) switching characteristics (ta = 0 ~ 70c, v cc = 5v 10%, v ss = 0v, unless otherwise noted, see notes 5, 12, 13) note 5: an initial pause of 500 m s is required after power-up followed by a minimum of eight initialization ras cycles. the initialization cycles should be done either by ras -only refresh cycles or by cas before ras refresh cycles only. note the ras may be cycled during the initial pause. and any 8 ras or ras /cas cycles are required after prolonged periods (greater than 32ms) of ras inactivity before proper device operation is achieved. after the initialization cycles, ras should be kept either higher than v ih(min) or lower than v il(max) except ras transition time. 6: measured with a load circuit equivalent to 2 ttl loads and 100pf. 7: assumes that t rcd 3 t rcd(max) and t asc 3 t asc(max) . 8: assumes that t rcd t rcd(max) and t rad t rad(max) . if t rcd or t rad is greater than the maximum recommended value shown in this table, t rac will increase by amount that t rcd exceeds the value shown. 9: assumes that t rad 3 t rad(max) and t asc t asc(max) . 10: assumes that t cp t cp(max) and t asc 3 t asc(max) . 11: t off(max) and t oez(max) defines the time at which the output achieves the high impedance state (i out | 10 m a |) and is not reference to v oh(min) or v ol(max) . symbol parameter test conditions limits unit min typ max c i(a) input capacitance, address inputs v i = v ss f = 1mhz v i = 25mvrms 5pf c i(oe ) input capacitance, oe input 7pf c i(w ) input capacitance, write control input 7pf c i(ras ) input capacitance, ras input 7pf c i(cas ) input capacitance, cas input 7pf c i/o input/output capacitance, data ports 8pf symbol parameter limits unit m5m417400c-5,-5s m5m417400c-6,-6s m5m417400c-7,-7s min max min max min max t cac access time from cas (note 6, 7) 13 15 20 ns t rac access time from ras (note 6, 8) 50 60 70 ns t aa column address access time (note 6, 9) 25 30 35 ns t cpa access time from cas precharge (note 6, 10) 30 35 40 ns t oea access time from oe (note 6) 13 15 20 ns t clz output low impedance time from cas low (note 6) 5 5 5 ns t off output disable time after cas high (note 11) 0 13 0 15 0 15 ns t oez output disable time after oe high (note 11) 0 13 0 15 0 15 ns
mitsubishi lsis m5m417400cj,tp-5,-6,-7,-5s,-6s,-7s fast page mode 16777216-bit (4194304-word by 4-bit) dynamic ram 5 timing requirements (for read, write, read-modify-write, refresh, and fast-page mode cycles) (ta = 0 ~ 70c, v cc = 5v 10%, v ss = 0v, unless otherwise noted. see notes 12, 13) note 12: the timing requirements are assumed t t = 5ns. 13: v ih(min) and v il(max) are reference levels for measuring timing of input signals. 14: t rcd(max) is specified as a reference point only. if t rcd is less than t rcd(max) , access time is t rac . if t rcd is greater than t rcd(max) , access time is controlled exclusively by t cac or t aa . t rcd(min) is specified as t rcd(min) = t rah(min) + 2t h + t asc(min) . 15: t rad(max) is specified as a reference point only. if t rad 3 t rad(max) and t asc t asc(max) , access time is controlled exclusively by t aa . 16: t asc(max) is specified as a reference point only. if t rcd 3 t rcd(max) and t asc 3 t asc(max) , access time is controlled exclusively by t cac . 17: either t dzc or t dzo must be satisfied. 18: either t cdd or t odd must be satisfied. 19: t t is measured between v ih(min) and v il(max) . read and refresh cycles note 20: either t rch or t rrh must be satisfied for a read cycle. symbol parameter limits unit m5m417400c-5,-5s m5m417400c-6,-6s m5m417400c-7,-7s min max min max min max t ref refresh cycle time 32 32 32 ms t rp ras high pulse width 30 40 50 ns t rcd delay time, ras low to cas low (note 14)183720452050ns t crp delay time, cas high to ras low 101010ns t rpc delay time, ras high to cas low 000ns t cpn cas high pulse width 10 10 10 ns t rad column address delay time from ras low(note 15)132515301535ns t asr row address setup time before ras low000ns t asc column address setup time before cas low(note 16)010010010ns t rah row address hold time after ras low 8 10 10 ns t cah column address hold time after cas low131515ns t dzc delay time, data to cas low (note 17) 0 0 0 ns t dzo delay time, data to oe low (note 17) 0 0 0 ns t cdd delay time, cas high to data (note 18) 13 15 15 ns t odd delay time, oe high to data (note 18) 13 15 15 ns t t transition time (note 19) 1 50 1 50 1 50 ns symbol parameter limits unit m5m417400c-5,-5s m5m417400c-6,-6s m5m417400c-7,-7s minmaxminmaxminmax t rc read cycle time 90 110 130 ns t ras ras low pulse width 50 10000 60 10000 70 10000 ns t cas cas low pulse width 13 10000 15 10000 20 10000 ns t csh cas hold time after ras low 506070ns t rsh ras hold time after cas low 131520ns t rcs read setup time after cas high 0 0 0 ns t rch read hold time after cas low (note 20) 0 0 0 ns t rrh read hold time after ras low (note 20) 10 10 10 ns t ral column address to ras hold time 25 30 35 ns t och cas hold time after oe low 131520ns t orh ras hold time after oe low 131520ns
mitsubishi lsis m5m417400cj,tp-5,-6,-7,-5s,-6s,-7s fast page mode 16777216-bit (4194304-word by 4-bit) dynamic ram 6 write cycle (early write and delayed write) read-write and read-modify-write cycles note 21: t rwc is specified as t rwc(min) = t rac(max) + t odd(min) + t rwl(min) + t rp(min) + 5t t . note 22: t wcs , t cwd , t rwd and t awd and, t cpwd are specified as reference points only. if t wcs 3 t wcs(min) the cycle is an early write cycle and the dq pins will remain high impedance throughout the entire cycle. if t cwd 3 t cwd(min) , t rwd 3 t rwd(min) , t awd 3 t awd(min) and t cpwd 3 t cpwd(min) (for fast page mode cycle only), the cycle is a read-modify-write cycle and the dq will contain the data read from the selected address. if neither of the above condition (delayed write) of the dq (at access time and until cas or oe goes back to v ih ) is indeterminate. symbol parameter limits unit m5m417400c-5,-5s m5m417400c-6,-6s m5m417400c-7,-7s min max min max min max t wc write cycle time 90 110 130 ns t ras ras low pulse width 50 10000 60 10000 70 10000 ns t cas cas low pulse width 13 10000 15 10000 20 10000 ns t csh cas hold time after ras low 506070ns t rsh ras hold time after cas low 131520ns t wcs write setup time before cas low (note 22) 0 0 0 ns t wch write hold time after cas low 8 10 10 ns t cwl cas hold time after w low 131520ns t rwl ras hold time after w low 131520ns t wp write pulse width 8 10 10 ns t ds data setup time before cas low or w low000ns t dh data hold time after cas low or w low 8 10 15 ns t oeh oe hold time after w low 131520ns symbol parameter limits unit m5m417400c-5,-5s m5m417400c-6,-6s m5m417400c-7,-7s min max min max min max t rwc read write/read modify write cycle time (note 21) 131 155 180 ns t ras ras low pulse width 91 10000 105 10000 120 10000 ns t cas cas low pulse width 54 10000 60 10000 70 10000 ns t csh cas hold time after ras low 91 105 120 ns t rsh ras hold time after cas low 546070ns t rcs read setup time before cas low 000ns t cwd delay time, cas low to w low (note 22) 36 40 45 ns t rwd delay time, ras low to w low (note 22) 73 85 95 ns t awd delay time, address to w low (note 22) 48 55 60 ns t cwl cas hold time after w low 131520ns t rwl ras hold time after w low 131520ns t wp write pulse width 8 10 10 ns t ds data setup time before w low 000ns t dh data hold time after w low 8 10 15 ns t oeh oe hold time after w low 131515ns
mitsubishi lsis m5m417400cj,tp-5,-6,-7,-5s,-6s,-7s fast page mode 16777216-bit (4194304-word by 4-bit) dynamic ram 7 fast-page mode cycle (read, early write, read-write, read-modify-write cycle) (note 23) note 23: all previously specified timing requirements and switching characteristics are applicable to their respective fast page mode cycle. 24: t ras(min) is specified as two cycles of cas input are performed. 25: t cp(max) is specified as a reference point only. cas before ras refresh cycle (note 26) note 26: eight or more cas before ras cycles instead of eight ras cycles are necessary for proper operation of cas before ras refresh mode. self refresh specifications self refresh devices are denoted by s after speed item, like -5s/-6s/-7s. the other characteristics and requirements than the below are same as normal devices. electrical characteristics (ta = 0 ~ 70c, v cc = 5v 10%, v ss = 0v, unless otherwise noted) (note 2) symbol parameter limits unit m5m417400c-5,-5s m5m417400c-6,-6s m5m417400c-7,-7s min max min max min max t pc fast page mode read/write cycle time 35 40 45 ns t prwc fast page mode read write/read modify write cycle time 76 85 95 ns t ras ras low pulse width for read write cycle (note 24) 85 125000 100 125000 115 125000 ns t cp cas high pulse width (note 25) 8 12 10 15 10 15 ns t cprh ras hold time after cas precharge 30 35 40 ns t cpwd delay time, cas precharge to w low (note 22) 53 60 65 ns symbol parameter limits unit m5m417400c-5,-5s m5m417400c-6,-6s m5m417400c-7,-7s min max min max min max t csr cas setup time before ras low 101010ns t chr cas hold time after ras low 101015ns t rsr read setup time before ras low 101010ns t rhr read hold time after ras low 101015ns symbol parameter test conditions limits unit min typ max i cc8(av) average supply current from vcc slow-refresh cycle m5m417400c (s) cas before ras refresh cycling or ras cycling & cas 0.2v oe & we 0.2v or oe & we 3 v cc - 0.2v a 0 ~ a 10 0.2v 500 m a (note 5) or a 0 ~ a 10 3 v cc - 0.2v t ref = 128ms (2048 cycles) output = open t ras = t rasmin. ~ 1 m s i cc9(av) average supply current from vcc slow-refresh cycle m5m417400c (s) ras = cas 0.2v 200 m a (note 5) output = open
mitsubishi lsis m5m417400cj,tp-5,-6,-7,-5s,-6s,-7s fast page mode 16777216-bit (4194304-word by 4-bit) dynamic ram 8 timing requirements (ta = 0 ~ 70c, v cc = 5v 10%, v ss = 0v, unless otherwise noted, see notes 12, 13) self refresh entry & exit conditions 1. in case of distributed refresh the last / first full refresh cycles (2k) must be made within t ns / t sn before / after self refresh, on the condition of t ns 32ms and t sn 32ms. 2. in case of burst refresh the last / first full refresh cycles (2k) must be made within t ns / t sn before / after self refresh, on the condition of t ns + t sn 32ms. symbol parameter limits unit m5m417400c-5s m5m417400c-6s m5m417400c-7s min max min max min max t rass self refresh ras low pulse width 100 100 100 m s t rps self refresh ras high precharge time 90 110 130 ns t chs self refresh ras hold time -50 -50 -50 ns t rsr read setup time before ras low 101010ns t rhr read hold time after ras low 101015ns
mitsubishi lsis m5m417400cj,tp-5,-6,-7,-5s,-6s,-7s fast page mode 16777216-bit (4194304-word by 4-bit) dynamic ram 9 test mode set cycle note 27: the test mode function is initiated by a w and cas before ras cycle (wcbr cycle) as specified in timing diagram. the test mode function is terminated by either a cas before ras refresh cycle (cbr refresh cycle) or a ras only refresh cycle. during the test mode, the device is internally organized as 16-bits wide (1m bytes depth). no addressing of ca 0 and ca 1 is required. during a write cycle, data must be applied to all dq (input) pins. the data can be different between dq pins. the data on each dq pin is written into 4-bits memory cells, respectively. during a read cycle, each dq (output) pin shows the test result of the 4-bits, respectively. high state indicates that they are same. low state indicates that they are not same. during the test mode operation, only wcbr cycle can be used to perform refresh. symbol parameter limits unit m5m417400c-5,-5s m5m417400c-6,-6s m5m417400c-7,-7s min max min max min max t wsr w setup time before ras low 10 10 10 ns t whr w hold time after ras low 10 10 15 ns
mitsubishi lsis m5m417400cj,tp-5,-6,-7,-5s,-6s,-7s fast page mode 16777216-bit (4194304-word by 4-bit) dynamic ram 10 timing diagrams read cycle (note 28)
mitsubishi lsis m5m417400cj,tp-5,-6,-7,-5s,-6s,-7s fast page mode 16777216-bit (4194304-word by 4-bit) dynamic ram 11 write cycle (early write)
mitsubishi lsis m5m417400cj,tp-5,-6,-7,-5s,-6s,-7s fast page mode 16777216-bit (4194304-word by 4-bit) dynamic ram 12 write cycle (delayed write)
mitsubishi lsis m5m417400cj,tp-5,-6,-7,-5s,-6s,-7s fast page mode 16777216-bit (4194304-word by 4-bit) dynamic ram 13 read-write, read-modify-write cycle
mitsubishi lsis m5m417400cj,tp-5,-6,-7,-5s,-6s,-7s fast page mode 16777216-bit (4194304-word by 4-bit) dynamic ram 14 ras -only refresh cycle
mitsubishi lsis m5m417400cj,tp-5,-6,-7,-5s,-6s,-7s fast page mode 16777216-bit (4194304-word by 4-bit) dynamic ram 15 cas before ras refresh cycle, slow refresh cycle
mitsubishi lsis m5m417400cj,tp-5,-6,-7,-5s,-6s,-7s fast page mode 16777216-bit (4194304-word by 4-bit) dynamic ram 16 hidden refresh cycle (read) (note 29) note 29: early write, delayed write, read write or read modify write cycle is applicable instead of read cycle. timing requirements and output state are the same as that of each cycle shown above. and in any cycle, t rsr & t rhr should be satisfied not to enter test mode.
mitsubishi lsis m5m417400cj,tp-5,-6,-7,-5s,-6s,-7s fast page mode 16777216-bit (4194304-word by 4-bit) dynamic ram 17 fast page mode read cycle
mitsubishi lsis m5m417400cj,tp-5,-6,-7,-5s,-6s,-7s fast page mode 16777216-bit (4194304-word by 4-bit) dynamic ram 18 fast page mode write cycle (early write)
mitsubishi lsis m5m417400cj,tp-5,-6,-7,-5s,-6s,-7s fast page mode 16777216-bit (4194304-word by 4-bit) dynamic ram 19 fast-page mode write cycle (delayed write)
mitsubishi lsis m5m417400cj,tp-5,-6,-7,-5s,-6s,-7s fast page mode 16777216-bit (4194304-word by 4-bit) dynamic ram 20 fast page mode read-write, read-modify-write cycle
mitsubishi lsis m5m417400cj,tp-5,-6,-7,-5s,-6s,-7s fast page mode 16777216-bit (4194304-word by 4-bit) dynamic ram 21 self refresh cycle
mitsubishi lsis m5m417400cj,tp-5,-6,-7,-5s,-6s,-7s fast page mode 16777216-bit (4194304-word by 4-bit) dynamic ram 22 test mode set cycle note 30: this cycle can be used for initialized cycle after power-up, however entried into test mode.

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